The present invention relates generally to semiconductor memory devices, and more particularly to a nonvolatile memory devices, systems and method of performing read and program operations.
Semiconductor memory devices may be classified as volatile and nonvolatile in the operative nature. Volatile semiconductor memory devices are generally characterized by high speed read and write operations, but lose stored data in the absence of applied power. In contrast, nonvolatile semiconductor memory devices retain stored data in the absence of applied power. Thus, the nonvolatile semiconductor devices are widely used in applications requiring data retention regardless of power supply state. There are many kinds of nonvolatile semiconductor memories, including as examples, mask read-only memories (MROMs), programmable ROMs (PROMs), erasable and programmable ROMs (EPROMs), electrically erasable and programmable ROMs (EEPROMs), etc.
However, MROMs, PROMs, and EPROMs do not allow ready update of stored data, since these memory types are not easily erased and written to. In contrast, data may be easily erased from and programmed to EEPROMs. As a result, EEPROMs are increasingly used in subsidiary data storage units and/or system programming tools where constant data updates are often required. Flash memory is one particular type of EEPROM that may be fabricated with much higher integration density than other types of EEPROMs. This characteristic makes flash memory ideal for use in applications like high-capacity subsidiary data storage units. Within the general category of flash type EEPROMs, NAND-type flash EEPROMs (hereinafter, referred to as “NAND flash memory”) is very advantageous in its great integration density, as compared to other types of the flash EEPROMs.
Like all semiconductor memories, flash memory is a particular form of integrated circuitry capable of receiving and storing (programming) digital data, and thereafter accessing and providing the stored data (reading). A flash memory device comprises an array of memory cells, where each memory cell is uniquely capable of storing data and providing the stored data upon request. Each memory cell may store a single bit (1-bit) of data or multiple bits (multi-bit) of data. Where 1-bit data is stored in a memory cell, the memory cell is conditioned in one of two threshold voltage distributions corresponding respectively to one of two data states ‘1’ and ‘0’. Where 2-bit data is stored in a memory cell, the memory cell is conditioned in one of four threshold voltage distributions each corresponding to one of four data states ‘11’, ‘10’, ‘01’, and ‘00’. Similarly, where 3-bit data is stored in a memory cell, the memory cell is conditioned in one of eight threshold voltage distributions each corresponding to one of eight data states ‘111’ through ‘000’. More recently, 4-bit flash memory cells are being investigated.
Various programming methodologies have been proposed for the programming of flash memory cells. The speed (i.e., the programming rate) and accuracy of these programming methods is very important to the overall operation of flash memory devices. Therefore, enhancing the programming rate is one important consideration in the further improvement of memory device and memory system performance.
In relation to flash memory devices, the so-called incremental step-pulse programming (ISPP) mode of programming memory cells has been used with good results. The ISPP mode operates to shift a flash memory cell towards a target threshold voltage by applying gradually increasing step pulses to a corresponding word line. Thus, the programming rate of an ISPP mode programming method is determined in part by the number of steps used. Reducing the number of incremental programming steps will increase the programming rate and help prevent over-programming of flash memory cells.